A tunable SiGe BiCMOS gain-equalizer for x-band phased-array RADAR applications

This paper presents a compact-size tunable gain-equalizer for X-Band Phased-Array RADAR applications in a 0.25μm SiGe BiCMOS technology. An isolated NMOS based variable resistance was used for the first time to tune the slope of the gain-equalizer. For NMOS, an isolated body created by a deep n-well was utilized to reduce insertion loss due to the substrate conductivity. Furthermore, the power-handling capability of the tunable gain-equalizer was improved thanks to the resistive body-floating technique. The designed tunable gain-equalizer operates in the frequency range from 8 to 12.5 GHz with a measured positive slope of 1 dB/GHz and 1 dB tunable slope. The effective chip area excluding the pads is 0.21 mm2, and the total area including pads is 0.31 mm2. To authors best knowledge, this study is the first tunable gain-equalizer in SiGe technology presented for X-band phased-array RADAR applications

Electrical Balance Duplexer Based In-Band Full Duplex System for 5G (28 GHz) Communication Systems

The evolution of wireless communication systems is witnessed every day by their users. Currently, 4G meets the needs of the users in terms of data-rate and latency. 4G is spreading to the world and dominating the worldwide market. However, ever-increasing user demands for higher data-rate, lower latency, and an increased number of users are generating new challenges that 4G could not manage to meet the demands. To overcome the challenges in 4G, the institutions are studying the next generation (5G) communication systems. With the introduction of 5G, the utilization of various new technologies such as full-duplex becomes necessary to meet the demand for higher data-rate and lower latency. With the in-band full-duplex operation, the spectrum e ciency is doubled theoretically. The improvements in the SiGe BiCMOS technology have made them be a good candidate for low-cost and high-performance transceivers. In this thesis, the design of an electrical balance duplexer based in-band full-duplex system for 5G (28 GHz) communication systems implemented in IHP's 0.13 m SiGe BiCMOS technology is presented. The electrical balance duplexer is constructed with a hybrid transformer and an impedance tuner to suppress the leakage from the transmitter to the receiver by reducing the mismatch between the antenna and balance port impedances. The duplexer achieves isolation between the transmitter and receiver sides more than 40 dB for various antenna impedances at 28 GHz. The transmitter gain of the system is more than 30 dB by achieving OP1dB of 12 dBm whereas the receiver gain of 5 dB is obtained. The minimum noise gure of the receiver is 8.2 d

A 8-18 GHz low noise variable gain amplifier with 30 dB gain control range

This brief presents a single-stage current steering, low noise variable gain amplifier with a novel amplitude and phase error reduction method. The design is implemented in IHP's 0.13 μm SiGe BiCMOS technology for 8-18 GHz. At the highest gain setting, S21 is 12.4 dB, the minimum noise figure is 1.93 dB, and the maximum input 1-dB compression point is 3.9 dBm. Fine gain control steps are achieved up to 30 dB with 0.5 dB increments. The maximum measured rms phase and amplitude errors are 12.3° and 0.49 dB, respectively. The proposed design consumes 24 mW DC power and occupies 0.58 mm2 including pads. To the best of the authors' knowledge, our work achieves the lowest noise figure and highest IP 1dB are achieved among the published variable gain amplifiers

A high-gain SiGe BiCMOS LNA for 5G in-band full-duplex applications

This paper presents a low noise amplifier (LNA) implemented in a SiGe BiCMOS technology for 5G applications. The LNA is based on a two-stage cascode amplifier topology with a differential input and single-ended output. The design of the first stage is pseudo-differential. The first stage is based on simultaneous noise and power matching technique. At the input, a balun for single-ended to differential-output conversion is located to enable single-ended measurements. The LNA achieves 25.3 dB of peak gain while dissipating 66 mW of power in small-signal operation. The input-referred 1 dB compression point and noise figure are-10 dBm and 2 dB measured at 25 GHz, respectively. This work achieves the highest FoM among the compared works attributed to the design of the two-stage cascode topology. The LNA occupies 1.35 mm2 including pads

A high linearity 6 GHz LNA in 130 nm SiGe technology

In this work, a high linearity LNA at 6 GHz with 1.15 dB NF, 27.7 dB gain is reported with IHP 130nm SiGe BiCMOS technology. The reported LNA achieves a highly linear performance and has -12.2 dBm IP1dB and 4.2 dBm IIP3. A two-stage cascode amplifier with inductive degeneration topology is used to obtain high gain. Optimum transistor biasing and sizing achieves an input matching without using any inductor which allowed low NF and high linearity. Additionally, custom, not PDK defined, transistor layouts have been created to decrease the core's parasitics to enhance the LNA's performance. LNA uses 3.3V as supply and consumes 98 mW DC power while occupying a 0.75 mm2 die area without pads. The reported LNA achieved one of the highest figures-of-merit among silicon-based LNAs and has comparable performance to SOI CMOS LNAs

A highly linear SiGe BiCMOS Gilbert-cell based downconversion mixer for 5G applications

In this brief a high linearity, low loss, downconversion mixer requiring low LO drive power is presented for use in 5G beamforming applications. The emitter degenerated Gilbert-cell mixer with a four-way power combiner, baluns, and output filter is implemented using a 130-nm SiGe BiCMOS technology. The measured input 1-dB compression point of the fully integrated mixer is 6.4 dBm with a conversion gain of -12.9 dB. The mixer consumes 29.7 mW during small-signal operation and has a core area of 0.99 mm2. The relatively low loss and high linearity performance of the core mixer makes it uniquely suitable for use in 5G receivers

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